1. Field of the Invention
The present invention relates to a semiconductor memory device, such as, for example, an SRAM (static random access memory).
2. Description of the Related Art
Most recent semiconductor integrated circuits receive an input signal through an input end thereof in an asynchronous state which does not depend on a clock signal, and execute an operation in response to the input signal at a relatively high frequency on the order of several tens of megahertz. A known example of such a semiconductor device is a semiconductor memory device referred to as an SRAM.
An SRAM includes a plurality of memory cells. The SRAM receives an address signal through an address end thereof and statically accesses a memory cell corresponding to the value of the received address signal so as to perform a read or write operation. Such an operation of the SRAM does not depend on a clock signal which indicates that the value of the address signal input to the address end is valid. Therefore, the read or write operation can be performed rapidly in response to the input address signal.
In the SRAM having the above-described structure, the timing at which the address signal is supplied may widely vary. In one example, after a series of address signals are supplied sequentially from the address end to the SRAM at a high speed of, for example, 20 MHz, a state of the signal which is input from the address end does not change for a relatively long time period. In a conventional SRAM in which a memory cell is accessed completely statically, the access to the memory cell selected in accordance with the value of the address signal supplied to the address end is maintained during the time period in which the state of the address signal does not change, unless the SRAM is controlled by another method using, for example, a chip select signal or an output enable signal.
In order to reduce an amount of power required for the relatively long time period in which the value of the address signal does not change (hereinafter, referred to as a xe2x80x9ctimeout periodxe2x80x9d) and improve an internal dynamic operating performance, most of the recent SRAMs include an address transition detection (ATD) circuit.
The ATD circuit detects a state transition of the signal which is input to an input end, especially an address end, of the SRAM, and generates an internal control signal in response to the detection of the state transition. The SRAM uses the ATD circuit in order to generate the internal control signal after the state transition of the address signal supplied to the SRAM is detected and before an address decoder accesses a desired memory cell. Thus, the SRAM can perform an internal operation such as, for example, a pre-charging operation of a bit line, and activation and deactivation of a sense amplifier. Such an internal operation may alternatively be performed after a prescribed timeout period passes in a cycle in which a memory cell is accessed (access cycle). When a new address signal is supplied to the SRAM, the ATD circuit detects a state transition of the address signal which is input to the address end and generates an internal control signal. Thus, the components of the SRAM which are necessary for the internal operations are activated, and a memory cell corresponding to the value of the new address signal is accessed.
When an address signal including a state transition at, for example, a high frequency is supplied to an SRAM or the like including the ATD circuit, a plurality of word lines in a memory array are undesirably selected and activated simultaneously regardless of whether the state transition is performed intentionally or occurs due to noise. This may undesirably result in that data stored in a memory cell of the SRAM is destroyed or a high level of current causes damage in the SRAM. In order to prevent the plurality of word lines from being simultaneously activated, it has been proposed that all the word lines be forcibly placed into an of f state (inactive state) during a time period in which the operation is in an equilibrium state in, for example, a second half of the access cycle. However, this conventional technique involves an undesirable possibility that a state transition of the address signal occurs before all the word lines are forcibly placed into the off state in the case where an input buffer circuit, provided for buffering the address signal supplied to the SRAM or other types of semiconductor memory devices, has a sufficiently high response speed. Therefore, this technique is not effective for preventing the plurality of the word lines from being simultaneously activated.
In order to solve these problems, Japanese Laid-Open Publication No. 6-176575, for example, discloses an input buffer circuit as shown in FIG. 4. The input buffer circuit shown in FIG. 4 is provided to each address end for receiving an address signal supplied to the SRAM or other types of semiconductor memory devices. The input buffer circuit includes an input stage 110, a delay circuit 116, a bus gate 118, an ATD circuit 120, and a latch 130.
The input stage 110 includes a terminal A for receiving an address signal, a terminal CE_ for receiving a chip enable signal, two P-channel pull-up transistors 112a and 112b, and two N-channel pull-down transistors 114a and 114b. A gate of one of the P-channel pull-up transistors 112a and a gate of one of the N-channel pull-down transistors 114a receive an address signal A1 (FIG. 5) from the terminal A. A gate of the other P-channel pull-up transistor 112b and a gate of the other N-channel pull-down transistor 114b receive a chip enable signal from the terminal CE_. An output end of the input stage 110 is connected to the delay circuit 116 and the ATD circuit 120 via inverters 113 and 115. The delay circuit 116 and the ATD circuit 120 each receive a signal B_ (FIG. 5) which is obtained by inverting the logic level of the address signal A1.
The delay circuit 116 outputs the signal B_ after a prescribed delay time period. An output end of the delay circuit 116 is connected to the bus gate 118 via an inverter 117, and the bus gate 118 receives a signal AD (FIG. 5) which is obtained by inverting the logic level of the signal B_ with a prescribed delay time period.
The ATD circuit 120 includes a delay gate 124a for directly receiving the signal B_ and a delay gate 124b for receiving the signal B_ via an inverter 123. The signal output from the delay gate 124a is input to one of two input terminals of a delay gate 126a. The signal output from the delay gate 126a is input to one of two input terminals of a delay gate 126b. The signal output from the delay gate 126b is input to one of two input terminals of a delay gate 126c. The other input end of the delay gate 126a, the other input end of the delay gate 126b, and the other input end of the delay gate 126c each receive the signal B_ via the inverter 123 and another inverter 125.
The signal output from the delay gate 126c via an inverter 129a (signal BD) is sent to one of two input terminals of a NAND gate 122a. As shown in FIG. 5, the signal BD is obtained by inverting the logic level of the signal B_. Specifically, a starting point of a pulse (falling edge) of the signal BD is delayed with respect to a starting point of a pulse (rising edge) of the signal B_ by a time period td.
Returning to FIG. 4, the other input end of the NAND gate 122a receives the signal B_ which is input to the ATD circuit 120. The signal output from the NAND gate 122a (signal P_) is sent to one of two input terminals of a NAND gate 128. As shown in FIG. 5, the signal P_ is kept in an inactive state for the time period td when both the signals B_ and BD are in an active state.
Referring to FIG. 4, the signal output from the delay gate 124b is input to one of two input terminals of a delay gate 126d. The signal output from the delay gate 126d is input to one of two input terminals of a delay gate 126e. The signal output from the delay gate 126e is input to one of two input terminals of a delay gate 126f. The other input end of the delay gate 126d, the other input end of the delay gate 126e, and the other input end of the delay gate 126f each receive the signal B, via the inverter 123, which is obtained by inverting the logic level of the signal B_.
The signal output from the delay gate 126f via the inverter 129b (signal BD_) is sent to one of two input terminals of a NAND gate 122b. As shown in FIG. 5, the signal BD_ is obtained by inverting the logic level of the signal B_. Specifically, a termination point of a pulse (falling edge) of the signal BD_ is delayed with respect to a termination point of a pulse of the signal B_ by the time period td.
The other input end of the NAND gate 122b receives the signal B. The signal output from the NAND gate 122b (signal P) is sent to the other input end of the NAND gate 128. As shown in FIG. 5, the signal P is kept in an inactive state for a time period in which both the signals B and BD_, which are input to the NAND gate 122b, are in an active state. Thus, a pulse signal ATD which is at a HIGH logic level during a prescribed time period is output from the NAND gate 128 in response to the state transition of the address signal A1 which is input to the input buffer circuit.
The bus gate 118 includes a P-channel transistor and an N-channel transistor which are connected in parallel. A gate of the P-channel transistor directly receives the pulse signal ATD from the ATD circuit 120, and a gate of the N-channel transistor receives the inverted pulse signal ATD via an inverter 121. The bus gate 118 is controlled by the pulse signal ATD output from the ATD circuit 120, and the bus gate is shielded from the latch 130 while the pulse signal ATD is output. An output end of the bus gate 118 is connected to the latch 130.
The latch 130 includes two inverters, i.e., a first inverter and a second inverter connected in a loop branch across the first inverter. An output of the latch 130 is connected to an output terminal AOUT of the input buffer circuit via an inverter 131. The output terminal AOUT is connected to an internal circuit (not shown) of the SRAM or other types of semiconductor memory devices.
An operation of the input buffer circuit will be described with reference to FIG. 5. FIG. 5 is a timing diagram illustrating waveforms of various signals input and output by various components in the input buffer circuit shown in FIG. 4.
During a time period from t2 to t4, the pulse signal ATD is output from the ATD circuit 120 and thus the bus gate 118 is shielded. Therefore, the latch 130 maintains the signal AD which is input for a time period from t0 to t1 before the state transition of the address signal A1 occurs. Thus, a signal A1OUT, which is in the same state as the signal before the state transition of the address signal occurs, is output to the internal circuit. When the time period in which the pulse signal ATD is at a HIGH logic level is terminated at time t4, a new post-state transition signal AD is supplied from the bus gate 118 to the latch 130. A post-state transition signal A1OUT is output to the internal circuit, such as, for example, an address decoder, a pre-charging circuit, or a memory cell.
During a time period from t5 to t10, since the pulse signal ATD is output from the ATD circuit 120, the bus gate 118 is shielded. Therefore, even when an accidental state transition of the address signal A1 occurs as does during a time period from t7 to t9, the signal AD is not input to the latch 130, and the latch 130 outputs a signal maintaining the previous state. Accordingly, such a short, accidental state transition can be prevented from influencing the signal which is output from the input buffer circuit. In FIG. 5, the dashed lines shown regarding the signal BD_ and the signal ATD represent the level which is obtained when the address signal output from the terminal A is at a HIGH logic level until the end of the delay time period td.
In the case where the input buffer circuit having the above-described structure is used for a general, conventional SRAM, the following phenomenon occurs. While the pulse signal ATD is at a HIGH logic level, the post-state transition address signal is not input to the address decoder, and the pre-state transition address signal which is maintained in the latch 130 is input to the address decoder and then decoded. During the time period in which the pulse signal ATD is at a HIGH logic level, an internal operation control signal which is generated based on the pulse signal ATD places the word line selected in an immediately previous access cycle into a non-selected state. After the pulse signal ATD becomes LOW, a new address signal is input to the address decoder and decoded, and a word line corresponding to the value of the new address signal is selected. As a result, even when a short, accidental state transition occurs to the address signal which is input to the input buffer circuit, the plurality of word lines can be prevented from being simultaneously activated as described above.
However, the technology described in Japanese Laid-Open Publication No. 6-176575 has the following problems.
The delay time period realized by the delay circuit 116 is set such that the state transition of the address signal A1 which is input to the terminal A does not reach the bus gate 118 before the bus gate 118 is shielded by the pulse signal ATD output from the ATD circuit 120. The pulse output from the ATD circuit 120 is delayed with respect to the state transition of the address signal A1 input to the terminal A by the delay time periods provided by the delay gates 124a, 124b, 126a, 126b, 126c, 126d, 126e and 126f. The delay time period realized by the delay circuit 116 is set as described above in order to prevent generation of race or competition conditions between the signal output from the delay circuit 116 and the signal output from the ATD circuit 120. In order for the state transition of the signal AD (FIG. 5) not to occur before the pulse signal ATD becomes HIGH, the time period from time t2 to t3 is adjusted by the delay circuit 116. The race or competition conditions cause an inappropriate operation of activating a plurality of word lines in a memory array.
When the pulse signal ATD becomes LOW, the new address signal is decoded by the address decoder. The timing of decoding needs to have a sufficient margin with respect to the internal operation of, for example, deactivating the word line corresponding to the value of the address signal which is input in the immediately previous access cycle, or stopping of the sense amplifier. In order to determine the timing of decoding, the race conditions between the time at which the pulse signal ATD becomes LOW and the time at which the internal operation is completed also need to be considered.
As described above, the conventional semiconductor memory device requires the following race conditions to be considered: (i) the race conditions between the time when the pulse signal ATD becomes HIGH and the time when the state transition of the signal AD output from the delay circuit 116 occurs, and (ii) the race conditions between the time when the pulse signal ATD becomes LOW and the time when the internal operation is completed. Such restriction regarding timings may undesirably influence the operating speed of the semiconductor memory device.
A semiconductor memory device according to the present invention includes a plurality of word lines and a plurality of bit lines arranged so as to cross each other; a memory cell provided at each of intersections of the plurality of word lines and the plurality of bit lines and connected to the corresponding word line, among the plurality of word lines, and the corresponding bit line, among the plurality of bit lines; an address transition detection circuit for detecting a state transition of an input address signal and generating a transition detection pulse signal; an address latch circuit for receiving the address signal and maintaining a value of the address signal; an address decoder for decoding the value of the address signal output from the address latch circuit, and selecting a word line corresponding to the value of the address signal among the plurality of word lines, and activating the selected word line; a pre-charging circuit for charging a bit line corresponding to the selected word line and the memory cell, among the plurality of bit lines; and a control signal generation circuit for receiving the transition detection pulse signal, and generating a decoder activating signal for activating the address decoder and a bit line pre-charging signal for controlling the pre-charging circuit. The address latch circuit is controlled by the bit line pre-charging signal, such that while the bit line pre-charging signal is at a first logic level, the address signal is input to the address latch circuit, and while the bit line pre-charging signal is at a second logic level, the input address signal is maintained by the address latch circuit. The address decoder is controlled to be activated by the decoder activating signal; and when the address decoder is activated, the word line corresponding to the value of the address signal input to the address decoder from the address latch circuit is activated, and the memory cell connected to the corresponding word line is accessed.
In one embodiment of the invention, the control signal generation circuit includes a first delay circuit, a second delay circuit, a third delay circuit, and a logic circuit. The first delay circuit receives the transition detection pulse signal, and outputs a signal having a termination point which is delayed with respect to the termination point of the transition detection pulse signal by a first delay time period. The second delay circuit receives the transition detection pulse signal, and outputs a signal having a termination point which is delayed with respect to the termination point of the signal output from the first delay circuit by a second delay time period. The third delay circuit receives the signal output from the first delay circuit, and outputs a signal, having a starting point which is delayed with respect to the starting point of the signal output from the first delay circuit by a third delay time period, as the bit line pre-charging signal. The logic circuit receives the transition detection pulse signal and also receives the signal output from the second delay circuit, and outputs the signal which is received from the second delay circuit as the decoder activating signal during a time period in which the transition detection pulse signal is in an inactive state.
In one embodiment of the invention, the first delay circuit, the second delay circuit, the third delay circuit and the logic circuit are timed to operate such that the bit line pre-charging signal is activated in the third delay time period after the decoder activating signal, which is output from the control signal generation circuit, is placed into an inactive state, and such that the decoder activating signal is placed into an inactive state while the transition detection pulse signal is in an active state.
In one embodiment of the invention, the third delay time period is set to be equal to or greater than a shortest possible time period between the time when an immediately previous access is terminated and thus the selected word line is placed into an inactive state and the time when a pre-charging operation of the bit line is started for a subsequent access in the case where the memory cells are continuously accessed after the address signal is input.
In one embodiment of the invention, the third delay time period is set to be equal to or greater than a shortest possible time period between the time when an immediately previous access is terminated and thus the selected word line is placed into an inactive state and the time when a pre-charging operation of the bit line is started for a subsequent access in the case where the memory cells are continuously accessed after the address signal is input.
In one embodiment of the invention, the first delay time period is set to be a time period which is required for the bit line pre-charging signal, generated based on the detection of a transition of the pulse signal, to have a pulse time period which is equal to or greater than a pre-charging time period required to perform the subsequent access to the memory cells.
In one embodiment of the invention, the second delay time period is set to be equal to or greater than a shortest possible time period between the time when the pre-charging operation of the bit line is completed and the time when the activation of the word line is started.
According to a general semiconductor memory device such as, for example, an SRAM, an internal operation control signal is generated based on an ATD pulse signal which is output from an ATD circuit. The internal operation control signal controls an internal operation such as, for example, a pre-charging operation of the bit line, the deactivation operation of the word lines, or the activation and deactivation of the sense amplifier. In order to prevent a plurality of word lines from being simultaneously selected and activated when the state transition of the address signal occurs, the timing at which the logic level of an internal operation control signal changes is adjusted by a delay circuit or the like to be independent from and not directly synchronized with the internal operation. Accordingly, in the conventional semiconductor memory device, the following race conditions, for example, need to be considered: (i) the race conditions between the starting point of the time period in which the ATD pulse signal is at a HIGH level and the time when the state transition of the signal AD output from the delay circuit occurs, and (ii) the race conditions between the termination point of the time period in which the ATD pulse signal is at a HIGH logic level and the time when the internal operation is completed. Thus, the conventional semiconductor memory device needs to be designed with a sufficient margin for variance in the characteristics caused by dispersion in the production process or the like.
According to the present invention, the bit line pre-charging signal, which is an internal operation control signal, controls the input of the address signal to the address latch circuit and maintenance of the address signal by the address latch circuit. The decoder activating signal controls the activation of the address decoder. Therefore, the timing at which the post-state transition address signal is decoded by the address decoder can be synchronized with the timing of the internal operation. Accordingly, the plurality of word lines can be prevented from being simultaneously activated, and the address signal can be supplied to the address decoder within a time period which is usually required for an internal operation, without considering the above-mentioned race conditions. Thus, the margin, which may undesirably influence the operating speed of the entirety of the semiconductor memory device, need not be provided.
Thus, the invention described herein makes possible the advantages of providing a semiconductor memory device capable of preventing a plurality of word lines from being simultaneously selected without influencing the operating speed of the semiconductor memory device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.